Flow Control - 2.0 English

RFSoC DFE PRACH LogiCORE IP Product Guide (PG391)

Document ID
PG391
Release Date
2024-05-30
Version
2.0 English

The DFE PRACH core does not support sample-by-sample flow control on the input data interface. The TVALID signal of the AXI4-Stream must be kept High constantly when the core is operational. When operating below the maximum capacity, for example because not all component carriers are active, the TVALID signal must be High even on cycles in which no valid data is being transferred. The TID signal (see Component Carrier Sequencing) is used to identify which bus cycles are carrying data samples belonging to active component carriers.

On the data output interface, m_axis_dout_tvalid is asserted to indicate that valid data is present on m_axis_dout_tdata on the current cycle. Due to the intermittent nature of the RACH captures and the low sample rate of captured PRACH traffic, the TVALID signal on this interface varies from clock cycle to clock cycle. The sequence of output samples is not generally predictable. Samples are output as soon as they are produced, and the PRACH channel and antenna they belong to are communicated by means of the TID signal.