Example Design - 2.0 English

RFSoC DFE PRACH LogiCORE IP Product Guide (PG391)

Document ID
PG391
Release Date
2024-05-30
Version
2.0 English

This chapter contains information about the DFE PRACH example design provided in the AMD Vivado™ Design Suite.

Note: The example design is provided for simulation purposes only. Synthesis, implementation, and bitstream generation are not supported. Use of the example design is only supported in Linux.