Dynamic Scheduling Control Ports - 2.0 English

RFSoC DFE PRACH LogiCORE IP Product Guide (PG391)

Document ID
PG391
Release Date
2024-05-30
Version
2.0 English

This interface is optional.

Port Name I/O Clock Description
s_axis_sched_tdata[31:0] I s_axis_aclk Scheduling control packet data.
s_axis_sched_tvalid I s_axis_aclk Valid handshake signal for the scheduling control channel.
s_axis_sched_tlast I s_axis_aclk Last framing signal for the scheduling control channel. Indicates the end of a control packet.
s_axis_sched_tready O s_axis_aclk Ready handshake signal for the scheduling control channel.