| m_axis_dout_tdata[32*NRL-1:0] |
O |
s_axis_aclk |
Output sample data. Width is determined by the number of PRACH
lanes NRL. The sample width is fixed at 16 bits per component (I and Q). |
| m_axis_dout_tvalid |
O |
s_axis_aclk |
Valid handshake signal for
the data output channel. The downstream logic uses this to identify cycles with
valid sample data present. |
| m_axis_dout_tid[7:0] |
O |
s_axis_aclk |
Transaction ID associated with the sample(s) on
s_axis_din_tdata. The lower four bits [3:0] indicate the RACH channel ID and the
upper four bits [7:4] indicate the associated antenna(s). See Table 1. |
| m_axis_dout_tlast |
O |
s_axis_aclk |
Last framing signal for
the data output channel. |
| m_axis_dout_tuser[UW-1:0] |
O |
s_axis_aclk |
User-defined framing information for the data output channel.
This is the latency compensated concatenation of the TUSER inputs for each band. The
width UW is the sum of the TUSER input widths over all bands. This port is legacy
and is now superseded by the m_axis_tbase interface. |