| Port Name | I/O | Clock | Description |
|---|---|---|---|
| s_axis_din1_tdata[2*IW*NL1-1:0] | I | s_axis_aclk | Input sample data. Width is determined by the input sample width IW (16 for 16-bit samples and 24 for 18-bit samples) and the number of antenna lanes NL1 where NL1=(Number of Antenna in band 1)/(Antenna Interleave factor for band 1). The sample width applies to both I and Q components. |
| s_axis_din1_tvalid | I | s_axis_aclk | Valid handshake signal for the data input channel. The upstream logic uses this to signal that it is providing data. |
| s_axis_din1_tready | O | s_axis_aclk | Ready handshake signal for the data input channel. Signal remains high unless the core is in reset. |
| s_axis_din1_tid[7:0] | I | s_axis_aclk | Transaction ID associated with the sample(s) on s_axis_din1_tdata. The lower four bits [3:0] indicate the antenna interleaving phase and the upper four bits [7:4] indicate the component carrier ID. |
| s_axis_din1_tlast | I | s_axis_aclk |
Last framing signal for
the data input channel. The core does not rely on this signal for operation. |
| s_axis_din1_tuser[UW1-1:0] | I | s_axis_aclk | User-defined framing information. Choose the width of this field when the core is configured. Used for triggering configuration updates within the core and aligning PRACH processing to the radio frame structure. |