The s_axis_din0_tdata, s_axis_din1_tdata, and s_axis_din2_tdata
input buses and the m_axis_dout_tdata output bus use
the same format for transferring sample data. The in-phase (I) part of each sample is
placed at the lowest-numbered bit position, followed by the quadrature (Q) part. Each
part of the sample is aligned to an 8-bit boundary. Add zero-padding above the
most-significant bit if the sample width is not a multiple of 8 bits.
If there is more than one lane, samples for multiple antennas are concatenated. The data for the lowest-numbered antenna is placed on the right-hand side (lowest-numbered bits), while the data for the highest-numbered antenna is on the left-hand side (highest-numbered bits).
The following figure shows the data format for both 16-bit and 18-bit sample widths.
The sample data is treated as two’s complement fixed-point data. The position of the binary point is arbitrary. This document assumes that the binary point is to the right of the MSB. This means there are 15 fractional bits when the sample width is 16-bit and 17 fractional bits when the sample width is 18-bit. The I and Q components of each input data item are taken to be the real and imaginary parts of one complex input sample.