Data Format - 2.0 English

RFSoC DFE PRACH LogiCORE IP Product Guide (PG391)

Document ID
PG391
Release Date
2024-05-30
Version
2.0 English

The s_axis_din0_tdata, s_axis_din1_tdata, and s_axis_din2_tdata input bus and the m_axis_dout_tdata output bus use the same format for transferring sample data. The in-phase (I) part of each sample is placed at the lowest-numbered bit position, followed by the quadrature (Q) part. Each part of the sample is aligned to an 8-bit boundary, with zero-padding added above the most-significant bit if the sample width is not a multiple of 8 bits.

Where the number of lanes is greater than one, the samples for the multiple antennas are concatenated with data for the lowest-numbered antenna on the RHS (lowest-numbered bits) and data for the highest-numbered antenna on the LHS (highest-numbered bits).

The figure below shows the data format for both 16-bit and 18-bit sample widths.

Figure 1. Data Format

The sample data is treated as two’s complement fixed-point data. The position of the binary point is arbitrary. In this document, it will be assumed that the binary point is to the right of the MSB, meaning there are 15 fractional bits when the sample width is 16-bit and 17 fractional bits when the sample width is 18-bit. The I and Q components of each input data item are taken to be the real and imaginary parts of one complex input sample.