Configuring RACH Extraction - 2.0 English

RFSoC DFE PRACH LogiCORE IP Product Guide (PG391)

Document ID
PG391
Release Date
2024-05-30
Version
2.0 English

The DFE PRACH core can process up to 16 PRACH channels at once. Every PRACH channel extraction operation occurs in parallel across all available antennas, for the RACH channel's source band. Each PRACH channel is associated with a component carrier (CC) and a band from which the PRACH must be extracted. To locate the radio slot boundaries within the incoming sample streams, the API requires the sub-carrier spacing and sample rate to be specified for each CC.

Allocation of PRACH channel processing across the available CCs is flexible. Two methods exist to control this: Static Scheduling through the API and Dynamic Scheduling through the Dynamic Control Packet. This section details how PRACH decimation is set for static timing. See Dynamic PRACH Scheduling for details on how the dynamic schedule operates.

The 5G NR standard allows up to eight PRACH frequency channels to be present within a single CC. For CCs with a lower bandwidth, a smaller number of channels is typical.

The initial decimation rate required to downsample the incoming CC data to Fc/16 MSPS for input to the PRACH processing chain is determined from the specified CC sample rate as described. It can be 1x, 2x, 4x, or 8x. The PRACH DDC can further decimate by 2x up to 24x according to the desired output sample rate for each RACH channel. The total decimation rate therefore ranges from 2x to 96x.

The API will examine the incoming CC sample rate to determine additional decimation rate from Fc/16 MSPS to get the total decimation rate for a given RACH channel. The API will then program this value into the core.

Once the incoming data has been down-sampled to Fc/16 MSPS, there are certain restrictions on the further decimation rate depending on the CC sample rate:

  • Further decimation from Fc/16 MSPS must follow the "30.72 MSPS" column from Table 1, if operating at 491.52 MHz or the "15.36 MSPS" column if the clock is specified to be operating at <491.52 MHz.
  • In addition, further decimation by 1x is permitted for FR2 and FR1 Seq Len of 1151 and 571.

In addition to the CC sub-carrier spacing parameter, the PRACH sub-carrier spacing is required to determine the NCO frequency. The spacing can be 1.25, 5, 7.5, 15, 30, 60, or 120 kHz.

The PRACH DDC chain incorporates a programmable gain stage at each of the six decimation stages. The gain available for the first five half-band stages is either 0 dB or 6 dB. The gain available at the final stage (2x or 3x decimation) is 0 dB, 6 dB, 12 dB, or 18 dB. The number of decimation stages used depends on the total decimation rate. The API allows the gain for each stage to be set individually.

For details of the data structure used by the API to capture the PRACH decimation parameters, see XDfePrach_DDCCfg.

No latency compensation is performed to account for the difference in processing delay and group delay between carriers with different DDC configurations. Latency adjustment is expected to be performed at the PRACH FFT processing stage.

The First in to First out latency varies depending upon the decimation rate. Also, the delay (in samples) from the first sample out to the "center" tap varies depending upon the decimation rate:

Table 1. Decimation Rate Effect on FIR Delays
Total Decimation Rate Impulse Response Length (in Input Samples) Impulse Response Length (in Output Samples) Output Samples to "center" of Impulse Response
Whole Output Samples Exact Delay
2 15 7 3 3.5
4 35 8 4 4.25
8 75 9 4 4.625
16 153 9 4 4.75
32 309 9 4 4.8125
3 47 15 7 7.667
6 99 16 8 8.1667
12 203 16 8 8.4167
24 409 17 8 8.5
48 821 17 8 8.54167
96 1645 17 8 8.5625