The DFE PRACH core has two clocks,
s_axis_aclk and s_axi_aclk.
The internal datapath logic (including the DFE PRACH primitive) and the data
input, data output, and dynamic scheduling control interfaces all operate synchronous to
s_axis_aclk. A typical frequency for this clock in a 5G
wireless system is 491.52 MHz.
Clock rates other than 491.52 MHz are supported. This can be used to provide alternative data rates, for example, clocking at 245.76 MHz will allow the use of a 15.36 MSPS channel. The frame tracking used in the core will adjust so that for a clock rate of 491.52 MHZ, 245.76 MHz and 122.88 MHz, the radio frame duration will be 10 ms.
The memory mapped AXI4-Lite interface
operates synchronous to s_axi_aclk. No timing relationship
between this clock and s_axis_aclk is assumed. The core can
now interface to a microprocessor bus which can run at a lower frequency than the
sample-processing frequency (for example, 250 MHz).