Block Delays - 2.0 English

RFSoC DFE PRACH LogiCORE IP Product Guide (PG391)

Document ID
PG391
Release Date
2024-05-30
Version
2.0 English

The following table shows the group delays introduced for each decimation value supported by the DFE PRACH core.

Table 1. Group Delays
Decimation Rate Number of Taps Group Delay to "center" of Output Response (in Samples)
FIR 0 FIR 1 FIR 2 FIR 3 FIR 4 FIR 5
2 N/A N/A N/A N/A N/A 15 3
4 N/A N/A N/A N/A 7 15 4
8 N/A N/A N/A 7 7 15 4
16 N/A N/A 5 7 7 15 4
32 N/A 5 5 7 7 15 4
3 N/A N/A N/A N/A N/A 47 7
6 N/A N/A N/A N/A 7 47 8
12 N/A N/A N/A 7 7 47 8
24 N/A N/A 5 7 7 47 8
48 N/A 5 5 7 7 47 8
96 5 5 5 7 7 47 8