Running the Example Design - 1.0 English

RFSoC DFE Fast Fourier Transform LogiCORE IP Product Guide (PG390)

Document ID
PG390
Release Date
2024-05-30
Version
1.0 English

To run the example design, select SIMULATION > Run Simulation > Run Behavioral Simulation from the Vivado Flow Navigator panel.

The example design contains finite state machines (FSMs) that generate data at the input of the FFT blocks and check that their output matches expectations. Input and output data files are provided for FFT and iFFT operations of 256 points and 4096 points. These files were generated using the bit-accurate C model of the RFSoC DFE FFT IP. The files use a simple ASCII format, making it simple to replace them with alternative stimulus vectors if required.

The input state machine controls both the AXI4-Stream control and data input interfaces. It sends both continuous data (TVALID always asserted) and discontinuous data (TVALID randomly toggling). Gaps can be inserted between data blocks. The TVALID probability and the length of the inter-block gaps are configurable via parameters in the example design source code.

The following figure shows the stages of an example design simulation.

Figure 1. Example Design Simulation