Resets - 1.0 English

RFSoC DFE Fast Fourier Transform LogiCORE IP Product Guide (PG390)

Document ID
PG390
Release Date
2024-05-30
Version
1.0 English

The RFSoC DFE FFT IP core has a single reset signal, s_axis_aresetn. This signal is active-Low and is synchronous to s_axis_aclk. It is used to reset the core to its default state. To achieve this, the reset signal should be asserted for at least two active clock cycles. The core is ready to accept new data on the first clock cycle following the deassertion of reset, but the initialization of the core's internal hard FFT primitive continues for 44 cycles after the core's reset is released. To minimize stalls and to ensure the lowest possible latency, it is therefore recommended that the first cycle of data input be provided no sooner than 44 cycles after s_axis_aresetn is deasserted.