| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family 1 | AMD Zynq™ UltraScale+™ RFSoC DFE |
| Supported User Interfaces | AXI4-Stream |
| Resources | Performance and Resource Use web page |
| Provided with Core | |
| Design Files | Encrypted RTL |
| Example Design | Verilog (simulation only) |
| Test Bench | Provided with the example design |
| Constraints File | Not Provided |
| Simulation Model | Encrypted Verilog C model |
| Supported S/W Driver | N/A |
| Tested Design Flows 2 | |
| Design Entry | AMD Vivado™ Design Suite |
| Simulation | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: N/A |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Xilinx Support web page | |
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