The behavior of the RFSoC DFE FFT Example Design can be configured by changing the following constants that appear at the top of the exdes_tb.sv file:
Parameter | Default Value | Description |
---|---|---|
NUM_BLOCKS_CONT_DATA_256 | 10 | Number of data frames of 256 samples sent when tvalid is continuous. Value can be set between 1 and 255. |
NUM_BLOCKS_CONT_DATA_256_4096 | 10 | Number of data frames alternating between 256 and 4096 samples sent when tvalid is continuous. Value can be set between 1 and 255. |
NUM_BLOCKS_DISC_DATA_256 | 10 | Number of data frames sent when tvalid is not continuous. Value can be set between 1 and 255. |
GAP_LENGTH | 2040 | Length in clock cycles of the gap between frames of data. |
TVALID_RANDOM_THRESHOLD | 25 | When random variable is above this threshold tvalid will be High. Value can be set between 'd0 (continuous tvalid) and 'd100. |
When the number of channels has been configured as a value greater than 1, identical data is sent on all channels in parallel.
The clock frequency generated by the example design test bench is based on the value set during generation of the RFSoC DFE FFT IP inside the Power Estimation Parameters. The default frequency is 491.52 MHz.