The RFSoC DFE FFT IP core uses a fixed-point number representation for input and output data. The binary point position is unimportant; the number of fractional bits (i.e., bits following the binary point) is the same on the output as it was on the input, whatever transform settings are used. Each complex data sample consists of an I sample in the lowest-numbered bits of the data bus, followed by an identically-formatted Q sample in the highest-numbered bits.

For example, `s_axis_din_tdata[15:0]`

is the real part (I)
of the input sample and `s_axis_din_tdata[31:16]`

is the imaginary part
(Q) of the input sample.

An FFT operation involves a succession of "butterfly" stages. At each stage,
the arithmetic operations required by the FFT algorithm lead to a growth in the number
of bits required to represent the intermediate results. Because the DFE FFT is
implemented using unscaled arithmetic, this bit-growth accumulates throughout the
processing chain and results in an output sample width that is wider than the input
sample width by log_{2}(N)+1 bits, where N is the point size of the transform.
For a 16-bit input width, the minimum output precision is 25-bit (for a 256-point FFT),
and the maximum output precision is 29-bit (for a 4096-point FFT).

Output data samples from the RFSoC DFE FFT IP core are sign-extended to a width of 29 bits (for FFTs smaller than 4096 points), and then zero-padded to a width of 32 bits.

For example, when a 1024-point FFT is performed, `m_axis_dout_tdata[26:0]`

is the real part (I) of the output sample and
`m_axis_dout_tdata[58:32]`

is the imaginary part (Q)
of the output sample. Bits 27 and 28 are sign-extended from bit 26, and bits 59 and 60
are sign-extended from bit 58. Bits 29, 30, 31, 61, 62, and 63 are all padded with
0.