Core Overview - 1.0 English

RFSoC DFE Fast Fourier Transform LogiCORE IP Product Guide (PG390)

Document ID
PG390
Release Date
2024-05-30
Version
1.0 English

The RFSoC DFE FFT core computes the discrete Fourier transform of one or more vectors of 2N complex numbers, where 8 ≤ N ≤ 12. Data input is in natural address order, and data output is produced in bit-reversed address order. Full arithmetic precision is maintained throughout the FFT processing chain.

Standard AXI4-Stream interfaces are used for data input and output. The data streams are capable of operating at up to 100% throughput. An AXI4-Stream interface is also provided for configuration and control of the core.

The core can support between one and eight parallel channels, each of which uses one DFE FFT custom hardware primitive to perform up to eight FFT operations simultaneously. When the DFE FFT core is generated with support for multiple channels, configuration and control parameters such as block size and transfer direction are common across all channels. The core has a single set of framing and flow control signals which are also common across all channels, meaning that the input sample index is identical on every channel and there is only a single output sample index which applies to every channel. Each channel processes one complex data sample per clock cycle.

The structure of the DFE FFT core is shown below.

Figure 1. DFE FFT Core Structure

The core supports an optional TREADY signal on the output data interface. When this option is selected, data flow through the FFT can be stalled on a cycle-by-cycle basis by the downstream logic. The output buffer block consumes more fabric resources in this mode.