AES Ports - 1.1 English - PG383

Advanced Encryption Standard (AES) Engine LogiCORE IP Product Guide (PG383)
Document ID
PG383
Release Date
2022-04-26
Version
1.1 English
Table 1. AES Ports
Port Name I/O Clock Description
key_valid I s_aclk Key valid pulse signal to indicate that metadata (key/IV) is valid.
key I s_aclk Key for encryption/decryption, must be valid when key_valid is asserted.
iv I s_aclk Initialization vector (IV) for encryption/decryption, must be valid when key_valid is asserted.
key_fetch O s_aclk Indication from core that it is ready to accept metadata (key/IV). Metadata is latched when both key_valid and key_fetch are asserted simultaneously.
s_aclk I Clock signal for the core.
s_aresetn I s_aclk Active-Low reset signal for the core.
s_axis_tvalid I s_aclk Input AXI4-Stream data valid signal.
s_axis_tdata I s_aclk Input AXI4-Stream data.
s_axis_tkeep I s_aclk Input AXI4-Stream signal to indicate which bytes in the data are valid.
s_axis_tlast I s_aclk Input AXI4-Stream signal to indicate last beat of the current packet.
s_axis_tready O s_aclk Output AXI4-Stream signal to indicate that the core is ready to consume another beat of data.
m_axis_tvalid O s_aclk Output AXI4-Stream data valid signal.
m_axis_tdata O s_aclk Output AXI4-Stream data.
m_axis_tkeep O s_aclk Output AXI4-Stream signal to indicate which bytes in the data are valid.
m_axis_tlast O s_aclk Output AXI4-Stream signal to indicate last beat of the current packet.
m_axis_tready I s_aclk Input AXI4-Stream signal to indicate that the core is ready to consume another beat of data.
xts_max_blk_err O s_aclk XTS Mode Error Indication when number of blocks/packets in a data unit crosses 220.
xts_same_key_err O s_aclk XTS Mode Error Indication when Key-1 and Key-2 within the same key are the same.