FLOW_EMPTY_AL Register (0x2274) - 1.0 English - PG381

Performance AXI Traffic Generator LogiCORE IP Product Guide (PG381)

Document ID: PG381
Release Date: 2023-10-18
Version: 1.0 English

Table 1. FLOW_EMPTY_AL Register (0x2274)
Bit	Default Value	Access Type	Description
31:13	0	RO	Reserved
12	0	RO	This bit is set when instruction BRAM is empty. This is used for infinite transactions. This register is updated with a new value until you send CAPTURE_ALL address along with Read enable. Otherwise, it holds the previous values till reset.
11	0	RO	This bit is set when Write channel instruction FIFO is empty. This is used for Infinite transactions. This register is updated with a new value until you send CAPTURE_ALL address along with Read enable. Otherwise, it holds the previous values till reset.
10	0	RO	This bit is set when Read channel instruction FIFO is empty. This is used for Infinite transactions. This register is updated with a new value until you send CAPTURE_ALL address along with Read enable. Otherwise, it holds the previous values till reset.
9	0	RO	If set, the TG has completed sending both Read and Write traffic. This is used for infinite transactions. This register is updated with a new value until you send CAPTURE_ALL address along with Read enable. Otherwise, it holds the previous values till reset.
8	0	RO	Both Read and Write traffic done. If set, TG has completed sending both Read and Write traffic. This is used for infinite transactions. This register is updated with a new value until you send CAPTURE_ALL address along with Read enable. Otherwise, it holds the previous values till reset.
7	0	RO	Write traffic done. If set, the TG has completed sending the Write traffic. This is used for infinite transactions. This register is updated with a new value until you send CAPTURE_ALL address along with Read enable. Otherwise, it holds the previous values till reset.
6	0	RO	Read traffic done. If set, the TG has completed sending the Read traffic. This is used for Infinite transaction. This register is updated with a new value until you send CAPTURE_ALL address along with Read enable. Otherwise, it holds the previous values till reset.
5	0	RO	This bit is set when Read channel FIFO is full. This is used for infinite transactions. This register is updated with a new value until you send CAPTURE_ALL address along with Read enable. Otherwise, it holds the previous values till reset.
4	0	RO	This bit is set when TG error occurs. This is used for infinite transactions. This register is updated with a new value until you send CAPTURE_ALL address along with Read enable. Otherwise, it holds the previous values till reset.
3	0	RO	Register bit is set High when Read request FIFO overflows. This is used for infinite transactions. This register is updated with a new value until you send CAPTURE_ALL address along with Read enable. Otherwise, it holds the previous values till reset.
2	0	RO	Register bit is set High when Read request FIFO underflows. This is used for infinite transactions. This register is updated with a new value until you send CAPTURE_ALL address along with Read enable. Otherwise, it holds the previous values till reset.
1	0	RO	Register bit is set High when Write request FIFO overflows. This is used for infinite transactions. This register is updated with a new value until you send CAPTURE_ALL address along with Read enable. Otherwise, it holds the previous values till reset.
0	0	RO	Register bit is set High when Write request FIFO underflows. This is used for infinite transactions. This register is updated with a new value until you send CAPTURE_ALL address along with Read enable. Otherwise, it holds the previous values till reset.