FLOW_EMPTY Register (0x2050) - 1.0 English - PG381

Performance AXI Traffic Generator LogiCORE IP Product Guide (PG381)
Document ID
PG381
Release Date
2023-10-18
Version
1.0 English
Table 1. FLOW_EMPTY Register (0x2050)
Bit Default Value Access Type Description
31:13 0 RO Reserved
12 0 RO This bit is set when instruction block RAM is empty.
11 0 RO This bit is set when Write channel instruction FIFO is empty.
10 0 RO This bit is set when Read channel instruction FIFO is empty.
9 0 RO If set, the TG has completed sending both Read and Write traffic.
8 0 RO Write traffic done.

If set, the TG has completed sending the Write traffic.
7 0 RO Read traffic done. If set, the TG has completed sending the Read traffic.
6 0 RO

This bit is set when Write channel FIFO is full.
5 0 RO This bit is set when Read channel FIFO is full.
4 0 RO This bit is set when a TG error occurs. Two things can cause the TG to update the error status bit to 1; these are Data Integrity Error and/or AXI Response Check Error.
3 0 RO Bit set High when Read request FIFO overflows.
2 0 RO Bit set High when Read request FIFO underflows.
1 0 RO Bit set High when Write request FIFO overflows.
0 0 RO Bit set High when Write request FIFO underflows.