A dead cycle (bubble) is an AXI clock cycle in which the VALID/READY handshake does not complete, so no data beat or addresses are transferred and the bus remains idle. It occurs whenever VALID or READY (or both) is low on a clock edge.
Example Scenario 1: PATG in AXI-MM Mode
1 transaction per instruction
3 instructions/commands written to BRAM
Figure 1. Used CSV Configuration
Figure 2. Waveform: PATG AXI-MM Mode Example Scenario 1
Result
- Transaction 1 -> Transaction 2: Dead clock cycles are 10
- Transaction 2 -> Transaction 3: Dead clock cycles are 9
Note: From next transaction
onwards dead clock cycles will be 9. If the 1 < transaction count < 8, dead
cycle count would vary.
Example Scenario 2: PATG in AXI-MM mode
8 transaction per instruction
3 instructions/commands written to BRAM
Figure 3. Used CSV Configuration
Figure 4. Waveform: PATG AXI-MM Mode Example Scenario 2
Result
The traffic generator produces transactions continuously with zero dead cycles between them.
| Transactions per Instruction | Result |
|---|---|
| 1 to 7 | Observable bubbles -- measured idle interval up to 10 clock cycles between transactions |
| >= 8 | No bubbles between beats -- if slave ready signal is not de-asserted |
Note:
WREADY and
AxREADY are generated by the AXI slave, not controlled by the
traffic generator/master. Therefore, their de-assertion represents slave-side
backpressure and should not be counted as source-generated dead cycles.