Transmit Resets - 2.0 English - PG371

Versal Adaptive SoC Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)
Document ID
PG371
Release Date
2025-12-03
Version
2.0 English
The transmit resets in the ILKNF subsystem are as follows:
c0_tx_reset
TX reset signal for the ILKNF subsystem. If asserted, this signal resets the TX protocol block and TX lanes of the ILKNF subsystem. Internally, this reset signal is synchronized to c0_axi_clk first and then to c0_core_clk. The resultant reset signal is then synchronized (in parallel) to tx_serdes_clk[0] (to be used in TX lane logic) and tx_alt_serdes_clk[0]. This reset signal is unused in FEC-only mode.
tx_serdes_reset[5:0]
For TX lanes configured in Interlaken mode, tx_serdes_reset[0] is the reset signal for TX lanes of the ILKNF subsystem. The tx_serdes_reset[0] signal should be held in reset until the transceiver PLL is locked and tx_serdes_clk[0] is stable. Internally, tx_serdes_reset[0] is synchronized (in parallel) to the tx_serdes_clk[0] and tx_alt_serdes_clk[0] clocks. The tx_serdes_reset[5:1] signal is unused in this mode. For TX lanes configured in FEC-only mode, tx_serdes_reset[5:0] are reset signals for six 100G FEC encoders. Both 50G slices of a 100G FEC share the same reset signal. The reset signal for each FEC core is synchronized (in parallel) to its corresponding tx_serdes_clk[5:0] and tx_alt_serdes_clk[5:0] clocks.

In Interlaken mode, on the TX path, c0_tx_reset and tx_serdes_reset[0] should be asserted at the same time. Note that asserting c0_tx_reset also resets the TX lanes. The safe practice for the reset sequence is to release c0_tx_reset first followed by tx_serdes_reset[0]. If, during the normal operation, tx_serdes_reset[0] is asserted, the ILKNF subsystem cannot recover without asserting c0_tx_reset reset and then releasing them based on the described reset sequence again.