The ILKNF reset structure consists of active-High reset signals for the SerDes, core logic, and a common AXI4-Lite reset. All resets are asynchronous inputs and are internally synchronized to the correct clock domain for use. When asserted, resets must be held for a minimum of 24 ns or 8 × the cycle time of the associated clock. In addition to pin-level resets, the ILKNF subsystem can be software reset through the AXI4-Lite accessible per-port reset registers.