Register Map - Register Map - 2.0 English - PG371

Versal Adaptive SoC Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)
Document_ID
PG371
Release_Date
2025-12-03
Version
2.0 English

You can access the following registers to control and view the statistics of the packet generator and monitor. All the given addresses are relative to the base address.

This register selects the segment in which to write. This register must be programmed before programming the RAM.

Table 1. GENSEGSEL: Generator Segment Selector Register (0x1000)
Bits Default Type Description
31:4 0x0000000 RO Unused bits
3:0 0x0 RW SEGMENT SELECT. Value 0 selects segment 0, 1 selects segment 1, 2 selects segment 2, and so forth.

This register is responsible for starting the packet transactions with Interlaken after programming the RAM entries and the number of repetitions.

Table 2. GENREPEATEN: Generator Repetition Enable Register (0x1040)
Bits Default Type Description
31:1 0x00000000 RO Unused bits
0 0 RW Packet transactions start on writing 1. This bit must be set to 0 after bit 0 GENREPEATDONE is set to 1.

This register is used to program the number of times the packet generator repeats the sequence of segmented AXI4 interface control signals that were written to the RAM. With every repetition the data sent varies but the control signals remain the same.

Table 3. GENREPEAT: Generator Repetitions Register (0x1044)
Bits Default Type Description
31:0 0x00000000 RW Number of repetitions . This register must only be written when the EN bit of the GENREPEATEN is a value of 0.

This register determines the last entry of a generator repetition. After enabled, the entries in the RAM are read from the first or 0th entry until the entry specified by this register. Then they are repeated. As entries are written beginning from 0, this entry contains the total number of entries minus 1. If there are only 5 entries, write 4 to this register.

Table 4. GENLAST: Generator Last Entry Register (0x1048)
Bits Default Type Description
31:0 0x00000000 RW Last entry to be read from the RAM

This register causes the generator statistics registers to be reset to zero.

Table 5. GENSTATSCLEAR: Generator Statistics Clear (0x1080)
Bits Default Type Description
31:1 0x00000000 RO Unused bits
0 0 WO CLEAR. Writing a value of 1 to this self-clearing bit causes all the statistics registers to be cleared.

This register contains the accumulated checksum.

Table 6. GENCHECKSUM: Generator Checksum (0x1090)
Bits Default Type Description
31:0 0x00000000 RO CHECKSUM. Contains the accumulated checksum of all valid bytes.

This register contains the accumulated byte count.

Table 7. GENBYTECOUNT: Generator Byte Count (0x1094)
Bits Default Type Description
31:0 0x00000000 RO TOTAL BYTE COUNT. Contains the accumulated number of valid bytes.

This register contains the accumulated channel sum.

Table 8. GENADDRSUM: Generator Address Sum (0x1098)
Bits Default Type Description
31:0 0x00000000 RO CHANNEL SUM. Contains the accumulated sum of all channels with SOP.

This register contains the accumulated SOP count.

Table 9. GENSOPCOUNT: Generator SOP Count (0x109C)
Bits Default Type Description
31:0 0x00000000 RO TOTAL SOP COUNT. Contains the accumulated number of valid SOPs.

This register contains the accumulated EOP count.

Table 10. GENEOPCOUNT: Generator EOP Count (0x10A0)
Bits Default Type Description
31:0 0x00000000 RO TOTAL EOP COUNT. Contains the accumulated number of valid EOPs.

This register contains the accumulated ERR count.

Table 11. GENERRCOUNT: Generator ERR Count (0x10A4)
Bits Default Type Description
31:0 0x00000000 RO TOTAL ERR COUNT. Contains the accumulated number of valid ERRs.

This register causes the statistics registers to be reset to zero.

Table 12. MONSTATSCLEAR: Monitor Statistics Clear (0x10C0)
Bits Default Type Description
31:1 0x00000000 RO Unused bits
0 0 WO CLEAR. Writing a value of 1 to this self-clearing bit causes all the statistics registers to be cleared.

This register contains the accumulated checksum.

Table 13. MONCHECKSUM: Monitor Checksum (0x10D0)
Bits Default Type Description
31:0 0x00000000 RO CHECKSUM. Contains the accumulated checksum of all valid bytes.

This register contains the accumulated byte count.

Table 14. MONBYTECOUNT: Monitor Byte Count (0x10D4)
Bits Default Type Description
31:0 0x00000000 RO TOTAL BYTE COUNT. Contains the accumulated number of valid bytes.

This register contains the accumulated checksum.

Table 15. MONADDRSUM: Monitor Address Sum (0x10D8)
Bits Default Type Description
31:0 0x00000000 RO CHANNEL SUM. Contains the accumulated sum of all channels with SOP.

This register contains the accumulated SOP count.

Table 16. MONSOPCOUNT: Monitor SOP Count (0x10DC)
Bits Default Type Description
31:0 0x00000000 RO TOTAL SOP COUNT. Contains the accumulated number of valid SOPs.

This register contains the accumulated EOP count.

Table 17. MONEOPCOUNT: Monitor EOP Count (0x10E0)
Bits Default Type Description
31:0 0x00000000 RO TOTAL EOP COUNT. Contains the accumulated number of valid EOPs.

This register contains the accumulated ERR count.

Table 18. MONERRCOUNT: Monitor ERR Count (0x10E4)
Bits Default Type Description
31:0 0x00000000 RO TOTAL ERR COUNT. Contains the accumulated number of valid ERRs.

This write-only register contains control bits to be written to RAM Entry N. To be used along with GENSEGSEL register to define the Segmented AXI4-Stream user interface control signals to be driven at clock cycle N. RAM Entry 0 would contain the signals to be driven at clock cycle 0 and so on.

Table 19. GENCTRL_E<N:> Generator Control Bits for Entry N (0x2000 + 4N)
Bits Default Type Description
31:17 - WO Unused bits
16:13 - WO MTY signal of Segmented AXI4-Stream Interface
12 - WO ERR signal of Segmented AXI4-Stream Interface
11 - WO EOP signal of Segmented AXI4-Stream Interface
10 - WO BCTL signal of Segmented AXI4-Stream Interface
9 - WO SOP signal of Segmented AXI4-Stream Interface
8 - WO EOP signal of Segmented AXI4-Stream Interface. Writing 0 to this register has no effect if segment 0 is selected.
7:0 - WO CHAN signal Segmented AXI4-Stream Interface.