Reduced Fabric Interface Rates Example 1 - 1.3 English - PG371

Versal Adaptive SoC Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

Document ID
PG371
Release Date
2025-05-29
Version
1.3 English

When the 24 x 25.78125 Gb/s configuration with 2048-bit AXI4-Stream interface is used and four lanes are decommissioned (that is, 20 x 25.78125 Gb/s), the AXI and core clocks need to be 303 MHz and 605 MHz respectively. If the same configuration is used and six lanes are decommissioned (that is, 18 x 25.78125 Gb/s), the AXI clock and core clock can run at lower frequencies of 228 MHz and 454 MHz respectively.