FEC-Only Example Design - 1.3 English - PG371

Versal Adaptive SoC Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)
Document ID
PG371
Release Date
2025-05-29
Version
1.3 English

You can open the FEC-Only example design through Vivado when the core is generated in the FEC-Only mode. You can view the hierarchy of the design below.

Figure 1. FEC-Only Example Design

Design Overview

The FEC-only example design consists of a traffigenerator, which connects to each TX FEC only interface. The data that this block generates encoded by the RS-FEC encoders present in ILKNF. Given each symbol is 10 bits long, an FEC sends data through the TX SerDes interface as follows:

  • In 100G mode, each FEC transmits 32 symbols per clock cycle through four tx_serdes_data pins, sending one codeword in 17 clock cycles.
  • In 50G mode, each slice in the FEC slice transmits 16 symbols per clock cycle through two tx_serdes_data pins, sending one codeword in 34 clock cycles.

An error injector located at the TX SerDes Interface injects a fixed or arbitrary number of errors in each codeword. The corrupted data is then passed to the RS FEC decoder though the RX SerDes interface, and then sent to the traffic checker at the RX FEC-only interface to assess the data integrity.

TX Traffic Generator

The TX traffic generator generates FEC frames with 4096 codewords, with each codeword having 5440 bits. The module consists of six segments, each of which transmits traffic for 100G KP4 FEC. Each segment can be split into two slices, A and B, to independently generate traffic for 50G KP4 FEC. You can use the following registers to configure the traffic generator.
Table 1. Register Information for Traffic Generator Configuration
Name Address Description
CTL_CFG_RATE_100G_REG 0x0024 A 6-bit register, where each bit configures both the slices of the corresponding segment to operate together at 100G mode.
CTL_CFG_RATE_1X50G_A_REG 0x0018 A 6-bit register, where each bit configures slice A of the corresponding segment to operate at 50G mode.
CTL_CFG_RATE_1X50G_B_REG 0x001C A 6-bit register, where each bit configures slice B of the corresponding segment to operate at 50G mode.
  1. All addresses mentioned in this section are relative to the base address of the register map (C_S_AXI_BASE_ADDR).

Each slice or segment can transmit a fixed number of frames as per its mode of operation. You can program this through CTL_CFG_NUM_FRAMES_REG (0x0020). End of the transmission is indicated by setting the corresponding bits in TX_DONE_REG (0x0330).

There are other control registers such as CTL_CFG_FECONLY_GAPS_EN_REG (0x0028), which inserts gaps between two consecutive codewords and CTL_CFG_FECONLY_SHORT_EN_REG (0x002C) which enables the generation of short codewords, that is, less than 5440 bits. These are not used with ILKN FEC.

RX Traffic Checker

The RX traffic checker module contains an instantiation of the TX generator. The output data of this instance is the same as the transmitted data, as the seed value of the internal PRBS generator remains the same as the TX traffic generator and hence there is a bit to bit comparison with the received data. While the control registers remain are same as the TX traffic generator, the following statistics are reported for each segment by the RX traffic checker and are stored in the following registers.
Table 2. RX Traffic Checker Registers
Name Address Description
DATA_MATCH_A_REG [N] 0x00A8 + N*0x20

100G Mode: The number of 320-bit words received that have matched with the transmitted data.

50G Mode: The number of 160-bit words received that have matched with the transmitted data.
DATA_MATCH_B_REG [N] 0x00B0 + N*0x20 50G Mode: The number of 160-bit words received that have matched with the transmitted data. Unused when the segment is in 100G mode.
DATA_MISMATCH_A_REG [N] 0x00B8 + N*0x20 100G Mode: The number of 320-bit words received that have not matched with the transmitted data.

50G Mode: The number of 160-bit words received that have not matched with the transmitted data.
DATA_MISMATCH_B_REG [N] 0x00C0 + N*0x20 50G Mode: The number of 160-bit words received that have not matched with the transmitted data. Unused when the segment is in 100G mode.
  1. N represents the segment number.
  2. All the above parameters are 64-bit values, whose higher order bits are stored in the subsequent memory location. For example the DATA_MATCH_A_REG[0] has its higher order bits stored in 0x00AC and so on.

Error Injector

The Error injector can corrupt a fixed or random number of 10-bit symbols in each codeword. You can control the probability with which a codeword can be corrupted. Use the following registers to control the error injector. For 100G mode, the controls given to SLICE A are applied to the codewords.
Table 3. Registers to Control the Error Injector
Name Address Description
CTL_CFG_ERRINJ_EN_FIXED_SYMERR_A_REG 0x0030 Setting bit N enables the injection of a fixed number of symbol errors in each codeword being received by slice 0 of FEC<N> in 50G mode and FEC<N> 100G mode.
CTL_CFG_ERRINJ_EN_FIXED_SYMERR_B_REG 0x0034

Setting bit enables the injection of a fixed number of symbol errors in each codeword received by slice 1 of FEC<N> in 50G mode. Unused in 100G mode.
CTL_CFG_ERRINJ_ALWAYS_CORRECTABLE_A_REG 0x0038 In case the number of symbol errors are not fixed, setting bit N of this register ensures that the number of errors inserted in each codeword being received by FEC<N> Slice 0 always less than 16. Applies to both slices in 100G mode.
CTL_CFG_ERRINJ_ALWAYS_CORRECTABLE_B_REG 0x003C In case the number of symbol errors are not fixed, setting bit N of this register ensures that the number of errors inserted in each codeword being received by FEC<N> Slice 1 is always less than 16. Unused in 100G mode.
CTL_CFG_ERRINJ_SYM_ERR_PER_CWA_REG [N] 0x0044 + N*0x10 The fixed number of symbol errors per codeword received by slice 0 of FEC<N> in 50G mode and by FEC<N> in 100G mode.

CTL_CFG_ERRINJ_SYM_ERR_PER_CWB_REG [N]

 0x0048 + N*0x10 The fixed number of symbol errors per codeword received by slice 1 of FEC<N> in 50G mode. Unused in 100G mode.
CTL_CFG_ERRINJ_CORRUPTION_PROB_A_REG [N] 0x004C + N*0x10 The value written to this register divided by 256 is the probability with which a codeword can be corrupted. Applies to slice 0 of FEC<N> in 50G mode and FEC<N> in 100G mode.
CTL_CFG_ERRINJ_CORRUPTION_PROB_B_REG [N] 0x0050 + N*0x10 The value written to this register divided by 256 is the probability with which a codeword can be corrupted. Applies to slice 1 of FEC<N> in 50G mode. Unused in 100G mode.
  1. When an FEC instance in ILKNF is configured to 50G, both slices of the FEC operate as independent FECs. CTL_CFG_ERRINJ_NO_INTERLEAVING_REG (0x0040) is to be written with 0x3F.
  2. CTL_CFG_ERRINJ_NO_INTERLEAVING_REG (0x0040) is to be written with 0x3F to observe results as per the above information during simulation or validation.

AXI4-Lite Register Map

The register map enables your to control and collect statistics from ILKNF, the traffic generator and checker and the error injector. It also provides access to the following statistics from Interlaken FEC. All addresses mentioned are relative to the base address or the C_S_AXI_BASE_ADDR parameter of the register map module.
Table 4. Interlaken FEC Statistics
Name Address Description
FEC<N>_SLICE0_CCW_REG 0x019C + N*0x4C Number of codewords corrected by Slice 0 of FEC<N> in 50G mode or FEC<N> in 100G mode.
FEC<N>_SLICE0_TCW_REG 0x01A0 + N*0x4C Total number of codewords processed by Slice 0 of FEC<N> in 50G mode or FEC<N> in 100G mode.
FEC<N>_SLICE0_UCW_REG 0x01A4 + N*0x4C Number of codewords Slice 0 of FEC<N> could not correct in 50G mode or FEC<N> in 100G mode.
FEC<N>_SLICE1_CCW_REG 0x01A8 + N*0x4C Number of codewords corrected by Slice 1 of FEC<N> in 50G mode. Unused in 100G mode.
FEC<N>_SLICE1_TCW_REG 0x01AC + N*0x4C Total number of codewords processed by Slice 1 of FEC<N> in 50G mode. Unused in 100G mode.
FEC<N>_SLICE1_UCW_REG 0x01B0 + N*0x4C Number of codewords which could not be corrected by Slice 1 of FEC<N> in 50G mode. Unused in 100G mode.
  1. When a FEC instance in ILKNF is configured to 50G, both slices of the FEC operate as independent FECs.
  2. N represents the ILKNF FEC instance number.

Calculating the Symbol Errors Seen by ILKN FEC

For a given FEC instance N, the total number of symbols corrupted are determined as follows.

  • Set the parameter C_ADDITIONAL_STATS of the register map module to 6’b111111.
  • Read and store data values from the addresses 0x174 + N*0x4C, 0x180 + N*0x4C, 0x18C + N*0x4C, 0x198 + N*0x4C and let them be E0, E1, E2, and E3.
  • Add the values obtained to get the total errors while using the FEC in 100G mode.
  • In case of 50G mode, the total errors seen by slice 0 is E0 + E1 while for slice 1 it is given by E2 + E3.