FEC-Only Encoder Interface Signaling for 100G Operation - 2.0 English

FEC-Only Encoder Interface Signaling for 100G Operation - 2.0 English - PG371

Versal Adaptive SoC Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

Document ID

PG371

Release Date

2025-12-03

Version

2.0 English

In 100G mode, the bit ordering for the input of the FEC0 encoder is as follows:

At the start of the codeword tx_fec0_slice0_din_start=1,
- tx_fec0_slice0_din[159:0]=CW[159:0]
- tx_fec0_slice1_din[159:0]=CW[319:160]
At the second codeword cycle,
- tx_fec0_slice0_din[159:0]=CW[479:320]
- tx_fec0_slice1_din[159:0]=CW[639:480]
At the third codeword cycle,
- tx_fec0_slice0_din[159:0]=CW[799:640]
- tx_fec0_slice1_din[159:0]=CW[959:800]
At the 17th codeword cycle,
- tx_fec0_slice0_din[159:0]=CW[5279:5120]
- tx_fec0_slice1_din[159:0]=CW[5439:5280]

In 100G mode, the bit ordering for the output of the FEC0 encoder is as follows:

At the start of the codeword tx_fec0_slice0_dout_start=1,
- tx_serdes_data0[79:0]=CW[79:0]
- tx_serdes_data1[79:0]=CW[159:80]
- tx_serdes_data2[79:0]=CW[239:160]
- tx_serdes_data3[79:0]=CW[319:240]
At the second codeword cycle,
- tx_serdes_data0[79:0]=CW[399:320]
- tx_serdes_data1[79:0]=CW[479:400]
- tx_serdes_data2[79:0]=CW[559:480]
- tx_serdes_data3[79:0]=CW[639:560]
At the third codeword cycle,
- tx_serdes_data0[79:0]=CW[719:640]
- tx_serdes_data1[79:0]=CW[799:720]
- tx_serdes_data2[79:0]=CW[879:800]
- tx_serdes_data3[79:0]=CW[959:880]
At the 17th codeword cycle,
- tx_serdes_data0[79:0]=CW[5279:5120]
- tx_serdes_data1[79:0]=CW[5279:5200]
- tx_serdes_data2[79:0]=CW[5359:5280]
- tx_serdes_data3[79:0]=CW[5439:5360]

The bit ordering for all 100G encoder interfaces is similar to FEC0. See the following table for a summary of 100G encoder bit ordering.

Table 1. 100G Encoder FEC-Only Bit Ordering Summary
FEC Inst	Encoder Input	Input CW Start Position	Encoder Output	Output CW Start Position
FEC0	tx_fec0_slice0_din[159:0] tx_fec0_slice1_din[159:0]	tx_fec0_slice0_din[0]	tx_serdes_data0[79:0] tx_serdes_data1[79:0] tx_serdes_data2[79:0] tx_serdes_data3[79:0]	tx_serdes_data0[0]
FEC1	tx_fec1_slice0_din[159:0] tx_fec1_slice1_din[159:0]	tx_fec1_slice0_din[0]	tx_serdes_data4[79:0] tx_serdes_data5[79:0] tx_serdes_data6[79:0] tx_serdes_data7[79:0]	tx_serdes_data4[0]
FEC2	tx_fec2_slice0_din[159:0] tx_fec2_slice1_din[159:0]	tx_fec2_slice0_din[0]	tx_serdes_data8[79:0] tx_serdes_data9[79:0] tx_serdes_data10[79:0] tx_serdes_data11[79:0]	tx_serdes_data8[0]
FEC3	tx_fec3_slice0_din[159:0] tx_fec3_slice1_din[159:0]	tx_fec3_slice0_din[0]	tx_serdes_data12[79:0] tx_serdes_data13[79:0] tx_serdes_data14[79:0] tx_serdes_data15[79:0]	tx_serdes_data12[0]
FEC4	tx_fec4_slice0_din[159:0] tx_fec4_slice1_din[159:0]	tx_fec4_slice0_din[0]	tx_serdes_data16[79:0] tx_serdes_data17[79:0] tx_serdes_data18[79:0] tx_serdes_data19[79:0]	tx_serdes_data16[0]
FEC5	tx_fec5_slice0_din[159:0] tx_fec5_slice1_din[159:0]	tx_fec5_slice0_din[0]	tx_serdes_data20[79:0] tx_serdes_data21[79:0] tx_serdes_data22[79:0] tx_serdes_data23[79:0]	tx_serdes_data20[0]