Customizing and Generating the Subsystem - 1.3 English - PG371

This section includes information about using AMD tools to customize and generate the subsystem in the AMD Vivado™ Design Suite.

If you are customizing and generating the subsystem in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl console.

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP subsystem using the following steps:

1. Select the IP from the IP catalog.
2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).

The following table shows the ILKNF IP presets supported in the Vivado IDE. You can choose the Start from scratch option in the presets drop-down to configure the IP to modes other than those mentioned in the following table. All configurations mentioned as per Table 1 and Table 1 are supported with GTM. For 112G and 106.25G GT line rates, the ILKNF hard block configuration is same as that of 53.125G/56.42G, while the SerDes data from two adjacent ILKN lanes, as shown in Table 1, is interleaved to form the data port of the GT interface.

For GTYP, configurations with a narrow SerDes interface are not supported with the exception of the 12.5G line rate. All possible configurations with a wide SerDes interface are supported but are subject to the availability of GTYP quads in close proximity to ILKNF.