To validate the example design, see the MRMAC Example Design Simulation and Validation Steps section in the Versal Devices Integrated 100G Multirate Ethernet MAC (MRMAC) LogiCORE IP Product Guide (PG314). The steps are similar for the DCMAC IP Example Design. This guide provides step-by-step instructions for the VPK120 example design such as:
- Simulating
- Synthesizing
- Implementing
- Validating
The following is the functionality involved in the generated C-code from the DCMAC IP Example Design.
- The
gt_rx_datapath_resetis applied multiple times to achieve the stable RX alignment from the core. By default, it is set to 10 iterations in the example design C-code, but you can modify to any value based on the requirement.
Before the validation process, ensure to check the loopback bit value in the
set_gt_pcs_loopback_and_reset() function. When
external loopback is required, take account of the cdrhold bit and set the loopback value to
3'h000. For GT Near-end PCS loopback, set the loopback to 3'h001. For detailed bit
information, check the generated C-code.