To validate the example design, refer to the MRMAC Example Design Simulation and Validation Steps section in the Versal Devices Integrated 100G Multirate Ethernet MAC (MRMAC) LogiCORE IP Product Guide (PG314), with step-by-step instructions to perform example design simulation, synthesis, implementation and validation of example design on VPK120. The steps are similar for DCMAC IP Example Design.
The following is the functionality involved in the generated C-code from the DCMAC IP Example Design.
Before validation process, make sure to check the loopback bit value in
the set_gt_pcs_loopback_and_reset() function. When
external loopback is required, take account of the cdrhold bit as well and set the loopback
value as 3'h000. For GT Near-end PCS loopback, set the loopback as 3'h001. For detailed bit information, check the generated
C-code.