Transmit Channel Flush in Independent MAC and PCS+FEC - 3.1 English - PG369

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2025-12-03
Version
3.1 English

The DCMAC Independent Mode MAC employs an internal time-sliced/channelized core. When adding or removing channels, it is not applicable to perform a global reset. Instead, individual channels can be reset/flushed/cleared independently. Channel flushes does not affect other active channels.

For TX channel flush, use the following procedure:

  1. On startup, keep tx_channel_flush High during TX data buffer linked list configuration.
  2. Disable pause insertion for the channel that is being flushed.
  3. Ensure there is no pending skip response for the channel that is being flushed (clear whatever is in the client logic that tracks pending skip responses to zero), so that it does not cause underflow after the channel is active again.
  4. Provide at least four valid cycles (with zero data) for that channel ID on the AXI bus.
  5. Check that tx_local_fault is asserted (and therefore channel context is clear).