Timer Adjustment Mechanisms - Timer Adjustment Mechanisms - 3.2 English - PG369

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) v3.2 LogiCORE IP Product Guide (PG369)

Document_ID
PG369
Release_Date
2026-07-22
Version
3.2 English

To provide time-of-day timestamps on the local clock (either a RX SerDes recovered clock or TX SerDes clock), the PTP/System Timer running on the DCMAC Subsystem local clock needs to be synchronized to the master time-of-day timer running on the system timer clock ( ts_clk_N). The DCMAC Subsystem system timer can be synchronized with a master timer in a number of methods. Each port has independent internal free-running system_timer per RX and TX. For the following description, the D variable must be substituted with the desired TX and RX direction target and the N variable must be substituted by the target port number.