Simulating the Example Design - Simulating the Example Design - 3.2 English - PG369

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) v3.2 LogiCORE IP Product Guide (PG369)

Document_ID
PG369
Release_Date
2026-07-22
Version
3.2 English

The example design provides a quick way to simulate and observe the behavior of the DCMAC IP subsystem example design projects generated using the AMD Vivado™ Design Suite.