Register Space - 3.1 English - PG369

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2025-12-03
Version
3.1 English

The DCMAC IP subsystem registers are accessible in a ZIP file. All registers are accessible through the AXI4-Lite interface.