Recognize Timing Critical Signals - 3.1 English - PG369

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)
Document ID
PG369
Release Date
2025-12-03
Version
3.1 English

The constraints provided with the example design identify the critical signals and timing constraints that need to be applied.