Receive Fixed Ethernet Startup Procedure When Reconfiguring (Not Using rx_core_reset) - 3.1 English - PG369

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2025-12-03
Version
3.1 English

The DCMAC FixedE path employs an internal time-sliced MAC that is a channelized core. When adding, removing, or reconfiguring ports, it is not applicable to perform a global reset (rx_core_reset). Instead, individual ports can be reset/cleared/flushed independently. Port flushes (and corresponding PHY resets) on reconfigured ports does not affect other active ports that are not being reconfigured.

  1. Assert rx_channel_flush and rx_serdes_reset on any active ports that are being reconfigured (or deactivated).
  2. Assert rx_channel_flush and rx_serdes_reset on any inactive ports that are being reconfigured to become active.
  3. Wait for 50 (minimum) core clock cycles or 25 APB3 cycles (when APB3 frequency is less than or equal to half of core clock rate – which is usual).
  4. Release rx_channel_flush for active ports.
  5. Wait for 50 (minimum) core clock cycles or 25 APB3 cycles (when APB3 frequency is less than or equal to half of core clock rate – which is usual).
  6. Release rx_serdes_reset for active ports.