The DCMAC FixedE path employs an internal time-sliced MAC that is a channelized
core. When adding, removing, or reconfiguring ports, it is not applicable to perform a
global reset (rx_core_reset). Instead, individual ports can be
reset/cleared/flushed independently. Port flushes (and corresponding PHY resets) on
reconfigured ports does not affect other active ports that are not being
reconfigured.
- Assert
rx_channel_flushandrx_serdes_reseton any active ports that are being reconfigured (or deactivated). - Assert
rx_channel_flushandrx_serdes_reseton any inactive ports that are being reconfigured to become active. - Wait for 50 (minimum) core clock cycles or 25 APB3 cycles (when APB3 frequency is less than or equal to half of core clock rate – which is usual).
- Release
rx_channel_flushfor active ports. - Wait for 50 (minimum) core clock cycles or 25 APB3 cycles (when APB3 frequency is less than or equal to half of core clock rate – which is usual).
- Release
rx_serdes_resetfor active ports.