The following describes the receive clocks in the DCMAC Subsystem.
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rx_axi_clk - AXI4-Stream interface clock. In addition, this clock is used for some statistics output ports.
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rx_core_clk - This internal high-speed clock drives the time-sliced MAC receive datapath.
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rx_serdes_clk[5:0] - These GT SerDes clocks are used for the receive PCS/FEC logic. There is one clock for each receive PHY port. These clocks are typically generated from the transceiver and provided to the IP.
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rx_alt_serdes_clk[5:0] - These clocks are used to receive data on the transceiver interface. These
clocks run at exactly half the
rx_serdes_clk[5:0]frequencies. These clocks are typically generated by the IP Wizard or transceiver. -
rx_flexif_clk[5:0] - These clocks are used by the flex interface. There is one clock for each receive PHY port.
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rx_macif_clk - This clock is used by the receive MAC interface.
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ts_clk[5:0] - These clocks are used for 1588 timestamping. There is one clock for each PHY port. The clocks are shared between TX and RX.