All primary AXI4-Stream interface signals are
little endian as required by 7. This
includes all tdata and tuser signals
(tuser_sopN, tuser_eopN,
tuser_mtyN, and tuser_errN). The exceptions are
the tx/rx_preamble signals. These signals are formatted as
big endian as they are passed directly to and from the DCMAC
PCS Encoder/Decoder.
This means that the first byte transmitted/received is
tx/rx_preamble[55:48] and the seventh byte transmitted/received is
tx/rx_preamble[7:0]. The SFD (0xD5) is
automatically added by the PCS Encoder/checked by the RX PCS Decoder (when enabled), is
the eighth transmitted/received preamble byte.