Flex Interface - 3.1 English - PG369

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)
Document ID
PG369
Release Date
2025-12-03
Version
3.1 English

The flex interface (FLEX I/F) is a series of tap points along the PHY/FEC datapath that allows external logic to connect to the internal hardened PCS resources as a PCS client with a full PCS state machine, a raw, scrambled PCS client (for example, transparent OTN mapping), or an unscrambled PCS with optional error block replacement (for example, FlexE mapping). 128GFC is also supported, along with direct access to the on-board FEC resources (including support for FlexO). The following diagram illustrates RX and TX functions in the path between the PCS lane alignment logic to the FLEX I/F port.

Figure 1. Flex Interface Tap Points
Note: See the DCMAC register map spreadsheet for the appropriate control setting to configure the various tap points.
Note: The PCS 64b/66b encoder and decoder exist to "sanitize" the 64b66b code block stream to and from the Flex Interface. Specifically, this block tracks the IEEE 802.3 Clause 49 state machine transitions to validate that the PCS transactions are legal. If an illegal transition is detected, the encoder/decoder inserts /E/ blocks into the datastream.

To support the multiple applications, each flex interface port has logic, and corresponding controls to enable/disable the descramble/scramble logic, alignment insertion/removal logic, invalid sync-header error block replacement, and PCS encoder/decoder logic.