The following figure shows the DCMAC example design with Legacy GT Wizard. In the block design, the DCMAC and GT Quad Base IP are connected along with the MBUFG_GTs. For more information on the GT Quad Base (Legacy GT Wizard) IP, see the Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331).
The following figure shows the DCMAC example design with GT Wizard Subsystem (gtwiz_versal IP). This example design is with the RTL instantiation of the GT IP. In the example design RTL design top, the DCMAC and GT Wizard IP are connected along with the MBUFG_GTs. For more information on the gtwiz_versal IP, see the Versal Adaptive SoC Transceiver Subsystem Product Guide (PG442).