DCMAC uses the Auto-Negotiation and Link Training (ANLT) block of GT Wizard subsystem IP for ANLT feature.
DCMAC multi-quad ANLT designs require independent TX clocking per quad because ANLT completes at different times. A master TX reset can affect completed lanes, so a TX FIFO must be placed between the DCMAC and each GT quad to support the separate TX clock domains. Also, for any multi-lane configuration with an individual line rate <100G, insert FIFOs in the RX data path between the DCMAC and GT for all lanes.
The following figure shows the DCMAC ANLT example design architecture.
For more information, see the Versal Auto Negotiation and Link Training Interface User Guide (UG1790) (registration required).