AXI4-Stream Interface Signaling for Channelized 400G Operation - AXI4-Stream Interface Signaling for Channelized 400G Operation - 3.2 English - PG369

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) v3.2 LogiCORE IP Product Guide (PG369)

Document_ID
PG369
Release_Date
2026-07-22
Version
3.2 English

Channelized segmented AXI4-Stream 400G operation uses a 1536-bit data bus with reduced clock frequency. The signaling is the same as in the table for Channelized 600G AXI4-Stream Interface Signaling.