The DCMAC Subsystem provides a significant amount of internal statistics/status gathering and accumulation for up to six MAC channels in addition to the six PHY ports. That internally stored information is accessible using the AXI4-Lite interface. For more details on the AXI4-Lite interface, refer to the AXI to APB Bridge LogiCORE IP Product Guide (PG073).
A complete description of the register map and the individual registers can be found in the Register Space section.