400GE for Ethernet Mode - 2.4 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)
Document ID
PG369
Release Date
2024-08-05
Version
2.4 English

Refer to 802.3-2022 - IEEE Standard for Ethernet for 400GBASE-R alignment marker encodings.

The custom alignment marker signals are used as follows for 400G.

Custom Signal Bits Usage
ctl_vl_marker_id0 [47:0] The 48 bits of Common Marker in the alignment marker {CM0, CM1, CM2, CM3, CM4, CM5}.
ctl_vl_marker_id1 [63:0] The upper 8 bits of the unique pad (UP0) of pcs lane 0 to 7. With pcs lane 0 at the highest 8 bits and pcs lane 7 at the lowest 8 bits.
{UP0 lane 0, UP0 lane 1, UP0 lane 2, UP0 lane 3, UP0 lane 4, UP0 lane 5, UP0 lane 6, UP0 lane 7}
ctl_vl_marker_id2 [63:0] The upper 8 bits of the unique pad (UP0) of pcs lane 8 to 15. With pcs lane 8 at the highest 8 bits and pcs lane 7 at the lowest 15 bits.
{UP0 lane 8, UP0 lane 9, UP0 lane 10, UP0 lane 11, UP0 lane 12, UP0 lane 13, UP0 lane 14, UP0 lane 15}
ctl_vl_marker_id3 [63:0] No used
ctl_vl_marker_id4 [63:0] Bottom 64 bits of alignment marker for pcs lane 0 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.
ctl_vl_marker_id5 [63:0] Bottom 64 bits of alignment marker for pcs lane 1 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.
ctl_vl_marker_id6 [63:0] Bottom 64 bits of alignment marker for pcs lane 2 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.
ctl_vl_marker_id7 [63:0] Bottom 64 bits of alignment marker for pcs lane 3 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.
ctl_vl_marker_id8 [63:0] Bottom 64 bits of alignment marker for pcs lane 4 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.
ctl_vl_marker_id9 [63:0] Bottom 64 bits of alignment marker for pcs lane 5 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.
ctl_vl_marker_id10 [63:0] Bottom 64 bits of alignment marker for pcs lane 6 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.
ctl_vl_marker_id11 [63:0] Bottom 64 bits of alignment marker for pcs lane 7 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.
ctl_vl_marker_id12 [63:0] Bottom 64 bits of alignment marker for pcs lane 8 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.
ctl_vl_marker_id13 [63:0] Bottom 64 bits of alignment marker for pcs lane 9 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.
ctl_vl_marker_id14 [63:0] Bottom 64 bits of alignment marker for pcs lane 10 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.
ctl_vl_marker_id15 [63:0] Bottom 64 bits of alignment marker for pcs lane 11 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.
ctl_vl_marker_id16 [63:0] Bottom 64 bits of alignment marker for pcs lane 12 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.
ctl_vl_marker_id17 [63:0] Bottom 64 bits of alignment marker for pcs lane 13 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.
ctl_vl_marker_id18 [63:0] Bottom 64 bits of alignment marker for pcs lane 14 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.
ctl_vl_marker_id19 [63:0] Bottom 64 bits of alignment marker for pcs lane 15 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}.
Example:

To set ctl_vl_marker_id4 . Bottom 64 bits of alignment marker for pcs lane 0 {UP1, UM0, UM1, UM2, UP2, UM3, UM4, UM5}. ctl_vl_marker_id4= {0xD9,0x01,0x71,0xF3,0x26,0xFE,0x8E,0x0C}