|
Core Specifics |
| Supported Device Family |
AMD Alveo™
U280 and U50(LV) Data Center accelerator cards
|
| Supported User Interfaces |
AXI4-Lite CSR
Interface |
| Resources |
DPU Configuration
|
| Provided with
Core
|
| Design Files |
Encrypted RTL |
| Example Design |
Verilog |
| Test Bench |
Not Provided |
| Constraints File |
Xilinx Constraints File |
| Simulation Model |
Not Provided |
| Supported S/W Driver
1
|
Xilinx Runtime (XRT) |
| Tested Design Flows
2
|
| Design Entry |
AMD Vitis™
unified software platform |
| Simulation |
N/A |
| Synthesis |
AMD Vivado™
Synthesis |
| Support |
|
Support web
page
|
-
AMD Vitis™
AI development flow.
- For the supported versions of the tools, see
the Linux OS and driver support information are available from the
Vitis
Unified Software Platform Documentation: Application
Acceleration Development (UG1393).
|