Hardware Architecture - 1.0 English

DPUCAHX8L for Convolutional Neural Networks Product Guide (PG366)

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The detailed hardware architecture of the DPUCAHX8L is shown in the following figure.

The HBM memory space is divided into virtual banks and system memory. The virtual banks are used to store temporary data and the system memory is used to store instructions, input images, output results, and user data. Following initialization, the DPU fetches instructions from system memory to control the operation of the computing engine. The AMD Vitis™ AI toolchain is leveraged to parse, quantize, and compile a trained model. The Vitis AI compiler is responsible to extract and compile the operators in the graph as a set of optimized micro-coded instructions which are executed by the DPU.

HBM is used to buffer weights, biases, intermediate feature maps, and output prediction metadata to achieve high throughput and efficiency.

Figure 1. DPU Hardware Architecture