The following figure shows the example system block diagram with the includes an AMD UltraScale+™ XCU280 FPGA and a PCIe® interface. Each implementation has one to two DPU cores and each DPU requires 2 GB HBM memory space. The DPU cores are integrated into the system through the AXI which connects to the HBM, and the whole system is integrated into the server through the PCIe interconnect. It could be used to perform deep learning inference tasks such as image classification, object detection, and semantic segmentation.
Figure 1. Example System with Integrated DPU
