The following table lists the DPU I/O signals and their function descriptions.
| Signal Name | Interface Type | Width | I/O | Description |
|---|---|---|---|---|
| s_axi_control | Memory mapped AXI slave interface | 32 | I/O | 32-bit memory mapped AXI interface for registers. |
| ap_clk | Clock | 1 | I | Kernel clock. The frequency of the clock should match the clock of the DPU core. The supported frequencies are 300 MHz, 275 MHz, and 250 MHz. |
| ap_clk_2 | Clock | 1 | I | Reference clock for the MMCM in the DPU. It is set to 100 MHz. |
| ap_rst_n | Reset | 1 | I | Active-Low reset for DPU general logic. |
| ap_rst_n_2 | Reset | 1 | I | Unused in the core. |
| DPU_SYS_M_AXI_00 | Memory mapped AXI master interface | 256 | I/O | 256-bit memory mapped AXI interface for system data. |
| DPU_SYS_M_AXI_01 | Memory mapped AXI master interface | 256 | I/O | 256-bit memory mapped AXI interface for system data. |
| DPU_SYS_M_AXI_02 | Memory mapped AXI master interface | 256 | I/O | 256-bit memory mapped AXI interface for system data. |
| DPU_VB_M_AXI_00 | Memory mapped AXI master interface | 256 | I/O | 256-bit memory mapped AXI interface for virtual bank data. |
| DPU_VB_M_AXI_01 | Memory mapped AXI master interface | 256 | I/O | 256-bit memory mapped AXI interface for virtual bank data. |
| DPU_VB_M_AXI_02 | Memory mapped AXI master interface | 256 | I/O | 256-bit memory mapped AXI interface for virtual bank data. |
| DPU_VB_M_AXI_03 | Memory mapped AXI master interface | 256 | I/O | 256-bit memory mapped AXI interface for virtual bank data. |
| DPU_VB_M_AXI_04 | Memory mapped AXI master interface | 256 | I/O | 256-bit memory mapped AXI interface for virtual bank data. |
| DPU_VB_M_AXI_05 | Memory mapped AXI master interface | 256 | I/O | 256-bit memory mapped AXI interface for virtual bank data. |
| DPU_VB_M_AXI_06 | Memory mapped AXI master interface | 256 | I/O | 256-bit memory mapped AXI interface for virtual bank data. |
| DPU_VB_M_AXI_07 | Memory mapped AXI master interface | 256 | I/O | 256-bit memory mapped AXI interface for virtual bank data. |
| interrupt | Interrupt | 1 | O | Active-High interrupt output from the DPU. |
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