The AXI Debug Hub core allows for the host runtime software (such as an AMD Vivado™ Hardware Manager) to communicate and interact with debug cores and features within an AMD Versal™ device. It provides an interface between the debug interface of a Versal device (such as JTAG or HSDP) and the debug cores within the programmable logic (PL) design.
The debug cores are directly attached to the debug hub core AXIS interfaces. However, debug hub uses an AXI interface to connect to the network on chip (NoC) of a Versal device or general purpose (GP) ports of the processing system (PS). After it is generated, the debug hub core is instantiated or added to the design.