Configurable FIFO - Configurable FIFO - 2.0 English - PG358

AI Engine LogiCORE IP Product Guide (PG358)
Document ID
PG358
Release Date
2024-11-18
Version
2.0 English

Configurable FIFOs are present to meet timing for transactions between the AI Engine and PL. They include register slices in the wrapper to handle backpressure while managing BLI for registered streams.

Table 1. Configurable FIFOs
Parameter Description Range Default Value
FIFO_TYPE_SI_AXIS* There are two options for the PL to AI Engine interface:
  • 0: original design (two deep)
  • 1: bypass the register slice
 0-1 0
FIFO_TYPE_MI_AXIS* There are five options for the AI Engine to PL interface:
  • 0: original design (six deep)
  • 1: fsm version (four deep)
  • 2: pointer version (four deep)
  • 3: fsm version (six deep)
  • 4: pointer version (six deep)
 0-4 0