|
Core Specifics |
| Supported Device Family
1
|
Versal®
ACAP |
| Supported User Interfaces |
Native |
| Resources |
N/A
|
| Provided with Core
|
| Design Files |
RTL |
| Example Design |
Verilog |
| Test Bench |
Verilog |
| Constraints File |
XDC |
| Simulation Model |
Not Provided |
| Supported S/W Driver |
N/A |
| Tested Design Flows
2
|
| Design Entry |
Vivado® Design Suite
|
| Simulation
3
|
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
| Synthesis |
Vivado Synthesis |
| Support |
| All Vivado IP Change Logs |
Master Vivado
IP Change Logs: 72775
|
|
Xilinx
Support web page
|
- For a complete list of supported devices, see
the Vivado IP catalog.
- For the supported versions of third-party
tools, see the Xilinx Design Tools: Release Notes
Guide.
- Behavioral simulations are supported with
Mixed Simulator Language. Netlist (post-synthesis and post-implementation)
simulations are supported with Verilog Simulator Language and are not supported by
Vivado Simulator.
|